046880 - תכן בעזרת מחשב של וי. ל. ס. י - אביב

Topic outline

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  CAD of VLSI Systems

  EE - 046880

  Spring 2012

  • News Forum
  • Student Forum
  • Partner Searching Forum
  • News forum
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  Topic 1

  Administration

  • Syllabus File
  • Hebrew Syllabus File
  • Administration File
  • Course Schedule File
  • Undergraduate URL
  • Graduate & Undergraduate Info (Heb) URL
  • Graduate & Undergraduate Info (Eng) URL
  • -
  • Exam Moed-A Time and Place ..............................(New!) URL
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  Topic 3

  Updated Lectures and Tutorials from the Current Semester

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  • Lectures:
  • Lecture 01 - Intro File
  • Lecture 02 - Modeling File
  • Lecture 03 - Verification File
  • Lecture 04 - Formal File
  • Lecture 05 - BDD File
  • Lecture 06 - BDD OPs File
  • Lecture 07 - FSMs File
  • Lecture 08 - Logic Synth 1 File
  • Lecture 09 - Logic Synth 2 File
  • Lecture 10 - Floorplan File
  • Lecture 11 - Routing File
  • Lecture 12 - Timing 1 File
  • Lecture 13 - Timing 2 File
  • Lecture 14 - Timing Synth File
  • _
  • Tutorials:
  • Tutorial 01 - VHDL x2 (new 20.03.2012bS) File
  • Tutorial 03 - Graphs File
  • Tutorial 04 - Simulation File
  • Tutorial 05 - URP File
  • Tutorial 06 - BDDs File
  • Tutorial 06 - BDDs - With Supelement (NEW!) (Please download) File
  • Tutorial 07 - BDD Algorithms File
  • Tutorial 08 - Optimization File
  • Tutorial 08 - BDD Algorithms (NEW!) (Some updates) File
  • Tutorial 09 - Simulated Annealing File
  • Tutorial 10 - Technology Mapping File
  • Tutorial 11 - Dynamic Programming (NEW!) - Corrected Version of Spring 2012 File
  • The Dynamic Programming tutorial-slides will be updated near the tutorial time.
  • Tutorial 11 - Dynamic Programming (Old!) File
  • Tutorial 12 - Power (NEW!) File
  • Tutorial 12 - Power (old) File
  • Tutorial 13 - Timing File
  • Tutorial 14 - Delay File
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  Topic 4

  Homework Assignments

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  • WET :
  • WET01 - VHDL File
  • Synopsis Design Analyzer manual File
  • WET02 - Compiled Code Simulator File
  • WET03 - Event Driven Simulator File
  • WET04 - CU-BDD File
  • WET05 - Simulated Annealing File
  • WET06 - Timing Verification File
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  • DRY :
  • DRY01 - Hardware Representation (bad version) File
  • DRY01 - Hardware Representation (fixed-01 version) File
  • DRY02 - Verification File
  • DRY03 - Boolean Functions File
  • DRY04 - BDDs File
  • DRY05 - Satisfiability File
  • DRY06 - Technology Mapping and Dynamic Programming File
  • DRY07 - Routing Time Model (Bad Version) File
  • DRY07 - Routing Time Model - FIXED Version File
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  • Misc' :
  • comp_code_example.pdf File
  • SYNOPSYS Instruction Manual File
  • Easy to Draw Gates for MS-Word File
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  • PAPER REVIEW :
  • Paper Review Assignment - Spring 2012 (NEW!) File
  • The Papers:
  • 2006 - Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs File
  • 2007 - GlitchMap An FPGA Technology Mapper for Low Power File
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  Topic 5

  Homework Submission

  • WET - Submission :
  • WET01 As (1/4) - VHDL - Submission Assignment (2.2)
  • WET02 As (1/4) - Compiled Code Simulator - Submission Assignment (2.2)
  • WET03 As (1/4) - Event Driven Simulator - Submission Assignment (2.2)
  • _
  • WET01 As (2/4) - VHDL - Submission Assignment (2.2)
  • WET02 As (2/4) - Compiled Code Simulator - Submission Assignment (2.2)
  • WET03 As (2/4) - Event Driven Simulator - Submission Assignment (2.2)
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  • WET02 As (3/4) - Compiled Code Simulator - Submission Assignment (2.2)
  • WET03 As (3/4) - Event Driven Simulator - Submission Assignment (2.2)
  • WET04 As (3/4) - CU-BDD - Submission Assignment (2.2)
  • WET05 As (3/4) - Simulated Annealing PDF document - Submission Assignment (2.2)
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  • WET05 As (4/4) - Simulated Annealing - Submission Assignment (2.2)
  • WET06 As (4/4) - Timing Verification PDF document - Submission Assignment (2.2)
  • WET05 (As Bonus) - Simulated Annealing - Submission Assignment (2.2)
  • WET06 (As Bonus) - Timing Verification PDF document - Submission Assignment (2.2)
  • DRY - Submission :
  • DRY01 (As - 1/4) - Hardware Representation - Submission Assignment (2.2)
  • DRY02 (As - 1/4) - Verification - Submission Assignment (2.2)
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  • DRY01 (As - 2/4) - Hardware Representation Assignment (2.2)
  • DRY02 (As - 2/4) - Verification Submission Assignment (2.2)
  • DRY03 (As - 2/4) - Boolean Functions - Submission Assignment (2.2)
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  • DRY03 (As - 3/4) - Boolean Functions - Submission Assignment Assignment (2.2)
  • DRY04 (As - 3/4) - BDDs - Submission Assignment (2.2)
  • DRY05 (As - 3/4) - Satisfiability - Submission Assignment (2.2)
  • DRY06 (As - 3/4) - Technology Mapping and Dynamic Programming - Submission Assignment (2.2)
  • DRY04 (As - 4/4) - BDDs - Submission Assignment (2.2)
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  • DRY05 (As - 4/4) - Satisfiability - Submission Assignment (2.2)
  • DRY06 (As - 4/4) - Technology Mapping and Dynamic Programming - Submission Assignment (2.2)
  • DRY07 (As - 4/4) - Routing TimeModel - Submission Assignment (2.2)
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  • DRY04 (As - Bonus) - BDDs - Submission Assignment Assignment (2.2)
  • DRY05 (As - Bonus) - Satisfiability - Submission Assignment Assignment (2.2)
  • DRY06 (As - Bonus) - Technology Mapping and Dynamic Programming - Submission Assignment (2.2)
  • DRY07 (As - Bonus) - Routing TimeModel - Submission Assignment (2.2)
  • Paper Review
  • Paper Review Assignment (2.2)
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  Topic 6

  Grades

  • Grades 02.07.2012 - W01,02, D01,02,03,04,05,06,07 File
  • Grades 02.07.2012 - All DRY and WET File
  • Grades 10.07.2012 - Exam Grades (Moed-A) File
  • Grades 11.07.2012 - Paper Review + Final Grades (Moed-A) File
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  Topic 7

  Papers and Links

  • 1998 - Fast Module Mapping and Placement for Datapaths in FPGAs File
  • 2004 - Placement and routing optimization for circuits derived from BDDs File
  • 2006 - High-Level Technique for Counteracting Leakagein Deep Sub-Micron File
  • 2006 - Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs File
  • 2008 - PaRS Fast and near-optimal grid-based cell sizing for library-based design File
  • 2009 - Dependent-Latch Identificationin Reachable State Space File
  • 2009 - Power Optimization With Power Islands Synthesis File
  • 2009 - Approximate BDD Minimization by Weighted A* File
  • 2009 - PaRS Parallel and Near-Optimal Grid-Based CellSizing for Library-Based Design File
  • 2011 - Coping with the Complexity of MicroprocessorDesign at Intel – A CAD History File
  • Power-Driven Flip-Flop Merging and Relocation File
  • SimPL: An Effective Placement Algorithm File
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  Topic 8

  Exams From Previous Years

  • More Exams File
  • More older Exams File
  • Note! - You might find more Exams material in the EE Library.
  • Exam_Moed_A_2010 File
  • Exam_Moed_A_2010 - Draft File
  • Exam_Moed_A_2010 - Solution File
  • .
  • Official Solution of Moed-A Exam of This Year
  • Exam_Moed_A_2011S - Solution File
  • Exam_Moed_A_2012S - Solution (draft) File